1. Field of the Invention
This present invention relates to high performance and low power CMOS circuits and, more particularly, to multi-threshold-voltage differential cascode voltage switch (DCVS) circuits.
2. Description of the Related Art
The most commonly used approach to achieve a low power design is to reduce power supply voltage V.sub.dd. However, in order to maintain performance, the threshold voltage (V.sub.t) should also be scaled down so that the overdrive (V.sub.g -V.sub.t) remains large enough. The delay for an inverter is approximately proportional to (V.sub.dd -V.sub.t).sup.-.alpha., where .alpha..apprxeq.=2 for long channel MOSFET devices. A reduction of V.sub.t causes an exponential increase in the subthreshold leakage current. As V.sub.dd and V.sub.t are scaled down, the increased leakage power can begin to dominate the dynamic switching power.
Differential cascode voltage switch (DCVS) logic is a dual-rail CMOS circuit technique which has advantages over single-rail traditional logic circuit techniques in terms of circuit delay, layout area and logic flexibility. A further advantage to DCVS circuits is the fact that they can be readily designed for a complex Boolean logic function within single gate delay using straightforward procedures based on Karnaugh maps and tabular methods. The logic function may also be synthesized. Static DCVS circuits may consume more power, however, than traditional CMOS circuits because the charging and discharging times depend on the turn-on and the turn-off paths within the DCVS tree and these are generally not symmetrical. This asymmetry prolongs the period of current flow through the latch of the DCVS circuit during the transient state, thus increasing the power dissipation. Dynamic DCVS circuits, such as NORA and DOMINO circuits, often suffer from accidental current discharge due to mismatches in pulldown times for drain nodes.
DCVS logic offers the opportunity to realize faster circuits than are possible with conventional forms of CMOS logic, but the speed advantage is gained at the expense of power consumption and accidental discharge. Therefore, a need exists for a DCVS circuit having low leakage and power dissipation, yet providing the increased speed over traditional CMOS logic circuits.